TWEVO's architecture

'Baseband processing' refers to the operations used to generate, codify, and protect data symbols (bit streams), which are conveyed and retrieved through analogue signals. TWEVO's architecture comprises several software-based baseband processing blocks.

At the lowest architecture level, the architecture adopts interconnecting FIFOs between each processing block, reducing the signalling and control paths. This also allows the implementation of complex designs operating at higher clock rates. The figure below illustrates how each processing block has an associated FIFO which receives and delivers the data flow to the neighbour processing blocks. The adoption of such architecture allows the agile design, development and standalone testing of new processing blocks in the SDR baseband processing chain.

The building block in TWEVOS’s asynchronous architecture is comprised of a processing block and its associated FIFO.

At the radio level, the strict synchronicity of the OFDM transmitter and receiver will be limited to the ADC and DAC, which significantly relaxes the architecture timing constraints. Synchronicity between transceivers is achieved when the following conditions are met: firstly, the baseband transmitter must ensure that the DAC interfacing FIFO does not become empty; secondly, the ADC of the baseband receiver which is interfaced with a FIFO does not become full. Following this approach, the whole transceiver design has been built as a set of interconnected modules (one processing block and its FIFO) with similar interfaces, i.e., an SDR assembled in a “drag-and-drop” fashion.